Current mirror circuits are employed in a variety of applications, such as digital output driver/buffer circuits where a well defined or regulated current drive capability is required. One example of a digital (CMOS) output buffer where a current mirror is used to establish the current drive at the buffer output is described in the U.S. Pat. application to W.R. Young et al, Ser. No. 075,641, filed July 20, 1987, entitled "Controlled Switching CMOS Output Buffer" and now Pat. No. 4,818,901, and assigned to the assignee of the present application. In accordance with the configuration and operation of the buffer described in the Young et al application, an output driver transistor is controllably switched between first and second logic states (ON and OFF), such that when switched from its OFF state to its ON state, it operates in a constant current mode and serves to discharge the capacitance of its output load. When switched from its ON to its OFF state, the output transistor operates in a constant voltage mode. Because the output transistor is part of a current mirror circuit, its performance is dictated by its relationship to its associated mirror transistor.
More particularly, with reference to FIG. 1, the configuration of such a current mirror circuit is shown as including an output MOSFET Q0, the source of which is coupled to a first reference potential terminal (ground), the drain of which is coupled to an output terminal V0 and, via a diode-connected complementary transistor Q1, to a (high) reference potential terminal (+V). The gate of output transistor Q0 is coupled to the gate and source of a transistor Q2 and a current control regulating resistor element R1. The drain of transistor Q2 is coupled to the source of a transistor Q3, the drain of which is grounded and the gate of which is coupled to output terminal V0. Transistor Q3 is controllably gated ON and OFF to limit (interrupt) current flow during quiescent conditions. Resistor Rl is coupled to complementary transistors Q4 and Q5, the drain source paths of which are coupled in series between the high reference (+V) and ground, and the gates of which are coupled to an input terminal VIN.
The operation of the current mirror is such that current flow through output transistor Q0 is some predefined multiple of the current through transistor Q2, when each of transistors Q4, Q2 and Q3 is gated ON. In addition, resistor R1 is typically formed of a doped polysilicon line, the geometry of which is selected so that the current flow through transistors Q4, Q2 and Q3 is dictated by the magnitude of resistor Rl, rather than by the characteristics of the transistors in the serial circuit path.
When the output buffer of FIG. 1 is employed as part of a data processing system, it can be expected to encounter substantial output switching noise, commonly referred to as `ground bounce`, resulting from the sudden flow of current through the chip ground line when the buffer output is switched from a high to a low state. Depending upon the parameters of the buffer circuitry (as a consequence of wafer processing, temperature and power supply voltage) the magnitude of the ground bounce may be large enough to disrupt or interfere with device operations. As the demand for increasingly larger current switching capabilities (narrower current switching windows) are placed upon digital circuit designs, while still meeting limited area layout (semiconductor real estate) requirements, it can be seen that some mechanism must be provided for enabling the output transistor to switch larger currents without substantially increasing the occupation area or size of that particular component to achieve an enhanced current mirror function.
One possibility would be to merely reduce the magnitude of resistor R1, thereby increasing the current flow through transistor Q2 and thus causing a proportionally larger current to be mirrored in output transistor Q0. However, by only decreasing the magnitude of resistor R1, the current flow through components Q4, Q2 and Q3 is no longer predominantly controlled by the value of resistor R1, but becomes subject to variations in characteristics of the transistors, which are process and temperature dependent, so that the action of the current mirror will be influenced by such parameters in addition to the ratio of the channel widths of transistors Q0 and Q2.